A charge coupled imaging device, that is, a CCD type imaging device, has a well known floating diffusion type amplifier at the final stage of the imaging device. The floating diffusion type amplifier converts electric signal charges obtained by the photoelectric conversion in each pixel constituted of a photodiode and the like into a voltage signal. Such floating diffusion type amplifier produces reset noises at the reset operation performed after converting the electric signal charges of each pixel into the voltage signal. In order to reduce or eliminate the reset noises produced by the floating diffusion type amplifier, a well known correlated double sampling (CDS) technology is used for extracting only an image signal in which the reset noises are removed.
FIG. 8 schematically shows an example of a structure of a conventional charge coupled imaging apparatus which uses a charge coupled imaging device or image sensor having a floating diffusion type amplifier. The charge coupled imaging apparatus of FIG. 8 comprises a charge coupled imaging device 1, a buffer circuit 2, a signal processing integrated circuit (a signal processing IC) 21, an image signal processing circuit 8, and a drive pulse generating circuit 9. The charge coupled imaging device 1 is a CCD type imaging device and has the floating diffusion type amplifier not shown in the drawing. The signal processing IC 21 comprises a correlated double sampling circuit 22, an AGC circuit 23 and an A/D converter 24.
In the charge coupled imaging apparatus of FIG. 8, an output signal of the charge coupled imaging device 1 is supplied via the buffer circuit 2 to the correlated double sampling circuit 22 in the signal processing IC 21. The drive pulse generating circuit 9 drives the charge coupled imaging device 1 by supplying appropriate drive pulses thereto. The drive pulse generating circuit 9 also supplies two kinds of pulses, i.e., clamp pulses and sampling pulses 10, which are synchronized with the drive pulses for the charge coupled imaging device 1, to the correlated double sampling circuit 22. The correlated double sampling circuit 22 removes the reset noises of the floating diffusion type amplifier. An output signal of the correlated double sampling circuit 22 in which the reset noises are removed is supplied to the AGC circuit 23 and the amplitude of the output signal is adjusted to a predetermined magnitude. The A/D converter 24 converts an output signal of the AGC circuit 23 into a digital signal which is then supplied to the image signal processing circuit 8 to produce an output image signal.
As a practical method of implementing the correlated double sampling circuit 22, the correlated double sampling circuit 22, the AGC circuit 23 and the A/D converter 24 are integrated into one signal processing IC 21. The signal processing IC 21 is often constituted of a CMOS integrated circuit, because of a power consumption, an integration degree and the like.
FIG. 9 shows an example of a concrete circuit structure of the correlated double sampling circuit 22 and the like among various components of the signal processing IC 21 which is constituted of a CMOS integrated circuit. In FIG. 9, an output signal of the charge coupled imaging device 1 is supplied to a buffer circuit 2. The buffer circuit 2 is constituted of, for example, an emitter follower circuit and the like, and converts a high output impedance of the charge coupled imaging device 1 to a low output impedance. An output signal of the buffer circuit 2 is supplied, via a capacitor C11, to the correlated double sampling circuit 22 which is shown in a box of broken line in FIG. 9 and which is included in the signal processing IC 21 (FIG. 8).
In the correlated double sampling circuit 22, a MOS transistor TR11 and the capacitor C11 compose a clamping circuit, which clamping circuit clamps a reset potential portion in an output signal of the charge coupled imaging device 1 to a predetermined potential Vref by using clamp pulses supplied from the drive pulse generating circuit 9 (FIG. 8). The clamped output signal is then supplied to a buffer circuit 25, and an output signal of the buffer circuit 25 is supplied to a MOS transistor TR13. The MOS transistor TR13 and a capacitor C13 compose a sample and hold circuit which samples and holds a signal potential portion of the output signal of the buffer circuit 25, i.e., the output signal of the charge coupled imaging device 1, thereby an image signal is obtained which is supplied to, for example, a positive input, i.e., a non-inverted input of a subtracting circuit or subtracter 27.
A capacitor C12, a MOS transistor TR12, a buffer circuit 26, a MOS transistor TR14, and a capacitor C14 constitute a circuit having the same structure as the circuit constituted of the capacitor C11, the MOS transistor TR11, the buffer circuit 25, the MOS transistor TR13, and the capacitor C13. An input end of the capacitor C12 is grounded. This circuit is provided for removing an influence of the clamp pulses and the sampling pulses on the above-mentioned image signal supplied to the positive input of the subtracter 27. That is, the output of this circuit is supplied to a negative input or an inverting input of the subtracter 27, and is subtracted from the image signal inputted to the positive input terminal of the subtracter 27, so that an influence of the clamp pulses and the sampling pulses is removed.
In the above-mentioned conventional charge coupled imaging apparatus, the MOS transistor TR11 of the correlated double sampling circuit 22 and the capacitor C11 constitute a clamping circuit, and clamp the reset potential portions of the output signal of the charge coupled imaging device 1 to a predetermined potential Vref by using the clamp pulses supplied from the drive pulse generating circuit 9. As is well known, during periods of the reset potential portions of the output signal from the floating diffusion type amplifier of the charge coupled imaging device, there appear reset noises. The output signal voltage produced from signal electric charges is outputted by using, as a reference potential thereof, the reset potential which is varied by the reset noises. Therefore, as mentioned above, the rest potential portions of the output signal is clamped to the predetermined potential Vref and the reset potential portions are fixed to a constant value to remove the reset noises. Then, by sampling the output signal voltage portions which are produced from signal electric charges and which are outputted by using the constant value as a reference potential, it is possible to obtain an image signal from which the reset noises are removed.
The operation of clamping the reset potential portions to a constant potential value is performed during periods in which the MOS transistor TR11 is turned on by the clamp pulses. However, in order to completely remove the reset noises, it is necessary for the clamping circuit composed of the MOS transistor TR11 and the capacitor C11 to completely clamp the reset potential portions to the constant potential value Vref. Therefore, a time constant determined by the on-resistance of the MOS transistor TR11 and the capacitor C11 must be sufficiently small such that each of the reset potential portions is completely fixed to the constant potential value Vref within a time period corresponding to the pulse width of the clamp pulse.
However, because of the following reason, it is impossible to use the capacitor C11 having a small capacitance value. That is, an input terminal 4 of the correlated double sampling circuit 22 constituted of a CMOS integrated circuit has a parasitic capacitance caused by circuit components of the integrated circuit, that is, a parasitic capacitance caused by bonding pads, wirings, MOS transistors, buffer circuits and the like. Therefore, an input signal is divided by a dividing circuit constituted of the capacitor C11 and the parasitic capacitance, and, therefore, the input signal is attenuated by a ratio determined by the capacitance values of the capacitor C11 and the parasitic capacitance. In order to decrease an influence of the signal division caused by the capacitances to a negligible value, it is necessary to make an attenuation of the input signal equal to or smaller than approximately 1/100. Thus, it is necessary to make the capacitance value of the capacitor C11 sufficiently large, for example, approximately 100 times the parasitic capacitance such that an influence by the parasitic capacitance becomes negligible. Therefore, it is impossible to use the capacitor C11 having a small value.
When the capacitor C11 having a large capacitance is used, it is necessary to sufficiently decrease the on-resistance of the MOS transistor TR11. This is because, it is necessary to make the time constant determined by the on-resistance of the MOS transistor TR11 and the capacitance of the capacitor C11 so small that the reset potential portions are clamped to the constant potential Vref within the time period of the clamp pulse width.
Therefore, it is necessary to use a large size transistor as the MOS transistor TR11, so that the MOS transistor TR11 occupies a large area when the correlated double sampling circuit 22 is implemented by using a CMOS integrated circuit. Also, it is necessary that a reference voltage circuit for providing the constant potential voltage Vref to the capacitor C11 having a large capacitance has a large current supplying ability to avoid variation of the constant potential voltage Vref when the clamping is performed. Thus, the reference voltage circuit must be composed by using large size transistor or transistors, so that the reference voltage circuit occupies a large area in a CMOS integrated circuit. Further, in order for the reference voltage circuit to have a large current supplying ability, it is also necessary to lower an impedance of the reference voltage circuit in addition to enlarging a size thereof. Since the impedance is proportional to a current flowing through the circuit, it is necessary to supply a large bias current, such as approximately several milli-amperes. Therefore, power consumption of the reference voltage circuit becomes large. Still further, in order to drive the capacitor C11 having a large capacitance, it is necessary to couple the buffer circuit 2 having a large driving ability at the output of the charge coupled imaging device 1. Thus, it is necessary to supply a large bias current to the buffer circuit 2, so that power consumption of the CMOS integrated circuit becomes even larger.
In addition to those mentioned above, the conventional charge coupled imaging apparatus has the following drawbacks. Since the charge coupled imaging device is usually driven by drive pulses having a frequency of approximately several MHz through dozens MHz, the pulse width of the clamp pulse applied to the MOS transistor TR11 is very short, for example, several ns (nanoseconds) through ten and several ns. Also, in order to perform a complete clamping operation, it is necessary that the time constant determined by the on-resistance of the MOS transistor TR11 and the capacitance of the capacitor C11 is roughly equal to the pulse width of the clamp pulse. However, because of the above-mentioned disadvantages of the conventional correlated double sampling circuit which is fabricated in the CMOS integrated circuit, it is difficult to obtain such optimum value of the time constant determined by the on-resistance of the MOS transistor TR11 and the capacitance of the capacitor C11. Therefore, in the conventional noise reduction circuit including the correlated double sampling circuit and the like, it was difficult to sufficiently remove the reset noises and it was difficult to obtain an image signal having good quality.